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SV51012
2014.01.10
Supported JTAG Instruction
10-5
JTAG Instruction
HIGHZ
CLAMP
PULSE_NCONFIG
CONFIG_IO
JTAG Boundary-Scan Testing in Stratix V Devices
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Instruction Code
00 0000 1011
00 0000 1010
00 0000 0001
00 0000 1101
Description
? Sets all user I/O pins to an inactive
drive state.
? Places the 1-bit bypass register
between the TDI and TDO pins.
During normal operation, the 1-bit
bypass register allows the BST data
to pass synchronously through the
selected devices to adjacent devices
while tri-stating all I/O pins until a
new JTAG instruction is executed.
? If you are testing the device after
configuration, the programmable
weak pull-up resistor or the bus
hold feature overrides the HIGHZ
value at the pin.
? Places the 1-bit bypass register
between the TDI and TDO pins.
During normal operation, the 1-bit
bypass register allows the BST data
to pass synchronously through the
selected devices to adjacent devices
while holding the I/O pins to a state
defined by the data in the
boundary-scan register.
? If you are testing the device after
configuration, the programmable
weak pull-up resistor or the bus
hold feature overrides the CLAMP
value at the pin. The CLAMP value is
the value stored in the update
register of the boundary-scan cell
(BSC).
Emulates pulsing the nCONFIG pin low
to trigger reconfiguration even though
the physical pin is not affected.
Allows I/O reconfiguration (after or
during reconfigurations) through the
JTAG ports using I/O configuration
shift register (IOCSR) for JTAG testing.
You can issue the CONFIG_IO instruc-
tion only after the nSTATUS pin goes
high.
Altera Corporation
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